The present invention relates to semiconductor devices and, more specifically, to an improved tunnel field effect transistor with increased drive current and reduced gate induced drain leakage (GIDL).
As semiconductor devices continue to be scaled down in size, aspects of their components suffer performance degradation due to physical effects. Transistors, such as field effect transistors (FETs), typically suffer from a fundamental thermodynamic limit in the subthreshold swing, given by the thermal voltage, kT/Qe, where k is the Boltzmann constant, T is the absolute temperature of the transistor, and Qe is the quantum of electric charge. This swing in turn places a floor on the threshold voltage of transistors, and hence a limitation in power-supply voltage scaling. In semiconductors, the highest mobility and the highest tunnel rates do not occur in the same crystal orientation and direction. An example of a typical prior art FET 100 is shown in FIG. 1 and includes a substrate 110 connected to a ground, a source 120, a drain 130, and a gate 140. The source 120 and drain 130 each include a source region 122 and a drain region 132 formed in the substrate 110, such as by doping, and are connected to respective power supplies 124, 134. A gate 140 includes a layer of insulator 142 deposited over a channel region 150 of the substrate. The gate is connected to a gate power supply 144 such that, for an n-p-n transistor, when a potential is applied to the gate 140, the channel is narrowed or closed. The drive current of the FET is limited by the effective mass of the charge carriers and carrier scattering along a particular crystal orientation along the source-to-drain direction. Also, a gate induced drain leakage (GIDL) 160 arises from electrons tunneling when a gate voltage is applied. The magnitudes of the drive and GIDL currents depend on applied voltage, insulator thickness, materials employed, ambient and operating temperatures, and other factors.
Recently, a class of transistors based on tunnel generation of channel carriers at the source has been explored. These tunnel field effect transistors may demonstrate subthreshold swings in excess of kT/Qe by employing band-to-band tunneling for generation of the channel current, thereby avoiding the thermodynamic limitation imposed on conventional FETs.
For a tunnel field effect transistor built in a crystalline semiconductor, it is advantageous to choose a crystal orientation which maximizes the tunneling rate for generation of channel carriers, and it is further desirable to choose a crystal plane and orientation which maximizes the mobility of the channel carriers. In most crystalline semiconductors, however, the plane and direction offering the highest tunnel rates do not coincide with the plane and direction offering the highest channel mobility. Thus, there is a need for an improved tunnel field effect transistor with both high tunnel rates and high channel mobility.
As indicated above, drive current is maximized along the crystal orientation which has the lowest effective mass of charge carriers. Though this maximizes drive current, GIDL current also increases dramatically for transistors of a scale below about 50 nm. GIDL current grows exponentially as scale decreases such that GIDL becomes a significant problem, interfering with operation of the transistor and/or requiring more power to operate the transistor. Current designs, therefore, may not provide increased drive current while providing reduced GIDL currents. Increases in required power are a problem since the trend in device miniaturization is to demand lower power consumption, for example, to reduce heat output and, in the case of mobile devices, increase battery life. Thus, there is a need for a transistor with high on/drive current but with lower GIDL, particularly for transistors on a scale of less than about 50 nm and/or to allow higher operating frequencies.